1. Field of the Invention
This invention generally relates to a capacitor pair structure, and more particularly, to a capacitor pair structure that increases the match thereof.
2. Description of the Prior Art
Referring to FIG. 1A, a multi-layer stacked capacitor structure is illustrated. The first conductive layer 110 parallels to the third conductive layer 130 and connects to the third conductive layers 130 by a conducting wire to form an end of a multi-layer capacitor structure 100. The second conductive layer 120 parallels to the fourth conductive layer 140 and connects to the fourth conductive layer 140 by another conducting wire to form the other end of the multi-layer capacitor structure 100. Herein, the second conductive layer 120 is equidistantly inserted between the first conductive layer 110 and the third conductive 130 in parallel, and the third conductive layer 130 is equidistantly inserted between the second conductive layer 120 and the fourth conductive 140 in parallel, so that a so-called sandwich structure is formed and its capacitance in a unit volume increases through converging stray capacitance that exists among conductive layers. However, in terms of the downside of the first conductive layer 110 and the upside of the fourth conductive layer 140, the stray capacitance is also generated while other conductive layers paralleling to them, and further affects the operations of a circuit, especially, in high frequency. And, the quantity of the stray capacitance is a direct ratio to the areas of the conductive layers, that is, while the areas of the multi-layer stacked capacitor structure 100 increase, not only its capacitance increases, but also the stray capacitance outside its two ends also increases.
Referring to FIG. 1B, a fringe capacitor structure is illustrated. A plurality of conducting strips 112 and 114 are in parallel and interlace to each other to form the first conductive layer 110, and through appropriately connecting, the conducting strips 112 couple to adjacent conducting strips 114 to form fringe capacitors Cf. A plurality of conducting strips 124 and 122 are in parallel and interlace to each other to form the second conductive layer 120, and are over and in parallel to the corresponding conducting strips 112 and 114. Through appropriately connecting, the conducting strips 124 couple to adjacent conducting strips 122 to form fringe capacitors Cf, in the meanwhile, the conducting strips 122 and 124 respectively couple to the corresponding conducting strips 112 and 114 to form stray capacitors Cs. A plurality of conducting strips 132 and 134 are in parallel and interlace to each other to form the third conductive layer 130, and are over and in parallel to the corresponding conducting strips 124 and 122. Through appropriately connecting, the conducting strips 132 couple to adjacent conducting strips 134 to form fringe capacitors Cf, in the meanwhile, the conducting strips 132 and 134 respectively couple to the corresponding conducting strips 124 and 122 to form stray capacitors Cs. Similarly, a plurality of conducting strips 144 and 142 are in parallel and interlace to each other to form the fourth conductive layer 140 and also to form fringe capacitors Cf, at the same time, also to form stray capacitors Cs between the corresponding conducting strips 132 and 134. The rest conductive layers may be deduced by analogy. Finally, the maximum capacitance in a unit volume can be obtained through integrating all fringe capacitors Cf and stray capacitors Cs.
The well-known capacitor structures mentioned above describe a single capacitor as an independent unit. However, while a circuit requires a capacitor pair application, two independent capacitors are hence connected together. Doing in this way, it causes not only the waste of circuit layout, but also the instable match between the two capacitors. For example, a capacitor layout on a wafer periphery originally has a fixed proportion to another capacitor layout on the wafer center. However, the fixed proportion might be changed due to the slightly different thickness between the wafer periphery and the wafer center, or due to a high current circuit layout just beside any one of the capacitor layouts. In addition, the stray capacitance generated from the outside of the electrodes also interferes with the capacitor pair working in high frequency.
In view of the drawbacks mentioned with the prior art of capacitor pair structure, there is a continued need to develop a new and improved structure that overcomes the disadvantages associated with the prior art of capacitor pair structure. The advantages of this invention are that it solves the problems mentioned above.